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RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
| Full title: | RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design |
|---|---|
| ISBN: | 9781546776345 |
| ISBN 10: | 1546776346 |
| Authors: | Sutherland, Stuart |
| Publisher: | CreateSpace Independent Publishing Platform |
| Edition: | 1 |
| Num. pages: | 488 |
| Binding: | Paperback |
| Language: | en_US |
| Published on: | 2017-06-10T00:00:01Z |
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